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I am going to list all the published articles in Circuits Today which has got at least 15+ Comments. We consider these articles as really successful  and this list may be helpful for our daily readers to have further interaction; hence improve their knowledge.

1. Infrared motion detector circuit – Enjoys 1st position with 81 comments so far. This is a VERY HOT topic.

2. 150 Watt amplifier circuit -  Stands 2nd with 75 comments. Another HOT & Active topic.

3Automatic LED Emergency Light -  Now on 3rd position with 73 comments. This HOT discussion is on a race!

4. 100 Watt inverter circuit – 62 Comments

5. Long Range FM Transmitter – 52 Comments

6. Battery charger circuit using SCR – 50 Comments

7. Single Chip FM Radio circuit – (35)

8. 100 Watt sub woofer amplifier -(30)

9.  AM Transmitter circuit – (28)

10. Remote control tester circuit – (27)

11. Simple Water Level Indicator

12. Lead acid battery charger circuit

13. Fire alarm circuit

14. TV transmitter circuit

15. 2 km FM transmitter

16. Simple Electronic Combination Lock using IC LS 7220

17.  High & Low voltage cut-off with delay& alarm

18. Light activated switch circuit

19. 50 W transistor amplifier

20. Air flow detector circuit

So that’s it! 20 HOT& Active posts listed above. Choose one that you like and be a part of it!!

Understanding FPGA and CPLD

Introduction

In the earlier 60’s it was discrete logic used by electronic industry. The digital system would look like noodle like maze of wiring between components. Once it is built it will be difficult to do rework on it. Sometimes the designers would forget what they have designed for! Manufacturing such systems was very difficult and redesign will be so eye-shutting just like making a PCB every time we redesign. The chip manufactures resolved this issue by placing an unconnected array of AND-OR gates in a single chip device called a programmable logic device (PLD).

The PLD contains an array of fuses that could be blown open or left closed to connect various pins to each AND gate. We can program a PLD with a set of Boolean sum-of-product equations so tat would perform the needed logic functions for our system.

A CPLD contains a bunch of PLD blocks whose inputs and outputs are connected together by a global interconnection matrix. So a CPLD has two levels of programmability: each PLD block can be programmed, and then the interconnections between the PLDs can be programmed.

An FPGA takes a different idea. It has a clump of simple, configurable logic blocks arranged in an array with interspersed switches that can rearrange the interconnections between the logic blocks. Each logic block is individually programmed to perform a logic function (such as AND, OR, XOR, etc.) and then the switches are programmed to connect the blocks so that the complete logic functions are implemented.

Differences between FPGA and CPLD

FPGA

CPLD

Suited for timing circuit because they have more registers. CPLD is suited for control circuit because they have more combinational circuit.
Timing reports will be different if same code is synthesized many times. Timing reports will be same result.
FPGA can be used to high-end product CPLD can be used to low-end product
FPGA has more flexibility as well as design capacity. CPLD has less compared to FPGA regarding design complexity
FPGA can operate at very high speed CPLD has less
The FPGA are volatile in many cases, that’s way they need a configuration memory for working with programmed design. CPLD devices are not volatile. They contain flash or erasable ROM memory in all of cases.
FPGA could not work untill the configuration is done. The CPLD could work immediately after power up.
FPGA is RAM base. CPLD is ROM base.
FPGAs are “fine-grain” devices. That means that they contain a lot (up to 100000) of tiny blocks of logic with flip-flops. CPLDs are “coarse-grain” devices. They contain relatively few (a few 100′s max) large blocks of logic with flip-flops.
FPGAs have special routing resources to implement efficiently binary counters and arithmetic functions (adders, comparators…). CPLDs do not. CPLDs have a faster input-to-output timings than FPGAs (because of their coarse-grain architecture, one block of logic can hold a big equation), so are better suited for microprocessor decoding logic for example than FPGAs.
FPGAs can contain very large digital designs CPLDs can contain small designs only.

Architectures_CPLD_FPGA

Implementing a logic design with the FPGA or CPLD.

  1. Enter a description of the logic circuit using a hardware description language (HDL) such as VHDL or Verilog. This can also be done by drawing the design using a schematic editor.
  2. Use a logic synthesizer program to transform the HDL or schematic into a netlist. The netlist is a description of the various logic gates in the design and their interconnection behavior.
  3. Use the implementation tools to map the logic gates and interconnections into the FPGA. The configurable logic blocks in the FPGA can be further decomposed into look-up tables that perform logic operations. The CLBs and LUTs are closely linked with various routing resources. The mapping tool collects the netlist gates into groups that fit into the LUTs and then the place & route tool assigns the gate collections to specific CLBs while opening or closing the switches in the routing matrices to connect the gates together.
  4. Once the implementation phase is complete, a program extracts the state of the switches in the routing matrices and generates a bit stream where the ones and zeroes correspond to open or closed switches.
  5. The bit stream is downloaded into a physical FPGA chip (usually embedded in some larger system).  The electronic switches in the FPGA open or close in response to the binary bits in the bit stream.  Upon completion of the downloading, the FPGA will perform the operations specified by your HDL code or schematic.  You can apply input signals to the I/O pins of the FPGA to check the operation of your design.

VHDL Source CodeCredit: This article is compiled Mr.Sarath who is working as a VLSI Engineer in Nest Group of Companies.

Differences between FPGA and CPLD

FPGA

CPLD

Suited for timing circuit because they have more registers.

CPLD is suited for control circuit because they have more combinational circuit.

Timing reports will be different if same code is synthesized many times.

Timing reports will be same result.

FPGA can be used to high-end product

CPLD can be used to low-end product

FPGA has more flexibility as well as design capacity.

CPLD has less compared to FPGA regarding design complexity

FPGA can operate at very high speed

CPLD has less

The FPGA are volatile in many cases, that’s way they need a configuration memory for working with programmed design.

CPLD devices are not volatile. They contain flash or erasable ROM memory in all of cases.

FPGA could not work untill the configuration is done.

The CPLD could work immediately after power up.

FPGA is RAM base.

CPLD is ROM base.

FPGAs are “fine-grain” devices. That means that they contain a lot (up to 100000) of tiny blocks of logic with flip-flops.

CPLDs are “coarse-grain” devices. They contain relatively few (a few 100′s max) large blocks of logic with flip-flops.

FPGAs have special routing resources to implement efficiently binary counters and arithmetic functions (adders, comparators…). CPLDs do not.

CPLDs have a faster input-to-output timings than FPGAs (because of their coarse-grain architecture, one block of logic can hold a big equation), so are better suited for microprocessor decoding logic for example than FPGAs.

FPGAs can contain very large digital designs

CPLDs can contain small designs only.

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Transistor Phase Shift Oscillator

Transistor Phase Shift Oscillator

The circuit arrangement of a phase-shift oscilla­tor using N-P-N transistor in CE configuration is shown in figure. As usual, the voltage divider R1-R2 provides dc emitter base bias, RE and CE combination provides temperature stability and prevent ac signal degeneration and collector resistor RC controls the collector voltage. The oscillator output voltage is capacitively coupled to the load by Cc.

In case of a transistor phase shift oscillator, the output of the feedback network is loaded appreciably by the rela­tively small input resistance (hie) of the transistor. Hence, instead of employing voltage series feedback (as used in case of FET phase shift oscillator), voltage shunt feedback is used for a transistor phase shift oscillator, as shown in figure.In this circuit, the feedback signal is cou­pled through the feedback resistor R’ in series with the amplifier stage input resistance h^. The value of R’ should be such that when added with amplifier stage input re­sistance hie, it is equal to R i.e., R’ + hie = R.

Operation of Circuit

The circuit is set into oscillations by any random or variation caused in the base current, that may be either due to noise inherent in the transistor or minor variation in voltage of dc power supply. This variation in base current is amplified in collector circuit. The output of the amplifier is supplied to an R-C feedback network. The R-C network produces a phase shift of 180° between output and input voltages. Since CE amplifier produces a phase reversal of the input signal, total phase shift becomes 360° or 0° which is essential for regeneration or for sus­tained oscillations] The output of this network is thus in the same phase as the originally assumed input to the amplifier and is applied to the base terminal of the tran­sistor. Thus sustained variation in collector current between saturation and cut-off values are obtained. R-C phase shift network is the frequency determining network, as already explained in case of FET phase-shift oscillator.

Applications

The phase shift oscillator is well suited to the range of frequencies from several hertz to several hundred kilohertz (20Hz to 200 kHz), and so includes the audio frequency range (upto 20 kHz). For generating different audio-frequencies, variable air capacitors are employed as circuit elements in the phase-shift network. It is possible to vary the frequency in the range of about 1 : 10 because the range of capacitors can be varied in the ratio of 10 : 1 (typically from 40 p F to 450 p F). For variations of frequency over a large range, the three capacitors are usually ganged so as to vary the capacitance of the three capacitors si­multaneously. Such a variation keeps the input impedance to the phase-shift network con­stant and also keeps constant the magnitudes of β and αβ. Thus the amplitude of oscillations will remain unaffected as the frequency is adjusted. The phase-shift oscillator is operated in class A so as to keep distortion to the minimum. Frequency range from 20 Hz to 200 Hz, 200 Hz to 2 kHz, 2 kHz to 20 kHz and 20 kHz to 200 kHz can be obtained by using different set of resistors.

Phase-shift oscillators are not suitable for higher frequency operation because at higher frequency, the internal phase shift of the transistor and reduction in hfe cause difficulties in designing the circuit. The frequency of the oscillator cannot be changed easily.