Electronic Circuits and Diagram-Electronics Projects and Design

Double-Diffused MOS (DMOS) In this article, the Double-Diffused MOS (DMOS) structure is explained with a diagram. The working of Vertical DMOS Transistor is also explained in detail with its structural analysis and diagram. To know the basics of DMOS take a look at the following posts. TAKE A LOOK : SHORT CHANNEL MOS STRUCTURES The figure below shows a double-diffused MOS (DMOS) structure. The channel length, L, is controlled by the junction depth produced by the n+ and p-type diffusions underneath the gate oxide. L is also the lateral distance between the n+ p junction and the p-n substrate junction….

Short Channel MOS Structures This article discusses the different factors that limit the speed of a MOSFET. The common methods to reduce the parasitics like Scaled MOS (SMOS) and High-performance MOS (HMOS) is explained in detail with their structure and diagram. There are many factors that limit the speed of a MOSFET. Because of the parasitic capacitances and resistances, the change in the channel current and output voltage  occur slowly. This is due to the fact that when the input voltage at the gate input is changed, the parasitic capacitances must be either charged or discharged through a parasitic resistance….

NMOS Fabrication Process In this article the various steps needed for NMOS Fabrication are explained in detail along with diagrams. To know the basic IC Fabrication Techniques, click on the link below. TAKE A LOOK : IC FABRICATION TECHNIQUES There are a large number and variety of basic fabrication steps used in the production of modern MOS ICs. The same process could be used for the designed of NMOS or PMOS or CMOS devices. The gate material could be either metal or poly-silicon (as described in this article for NMOS device). The most commonly used substrate is bulk silicon or…

PMOS vs NMOS The advantages of n-channel MOSFET’s over p-channel MOSFET’s and vice versa have been explained in detail. Even the problems that NMOS faces in device processing and oxidation have also been explained. n-channel MOSFETs have some inherent performance advantages over p-channel MOSFET’s. The mobility of electrons, which are carriers in the case of an n-channel device, is about two times greater than that of holes, which are the carriers in the p-channel device. Thus an n-channel device is faster than a p-channel device. However, PMOS circuits have following advantages PMOS technology is highly controllable. It is a low…

MOSFET Technology and Various MOS Process This article focuses on basics of MOSFET Technology,basics of various MOS process like p-channel MOS (PMOS), n-channel MOS (NMOS), Complimentary MOS (CMOS) – its manufacturing, cross section, and other advantages of one over other. Most of the LSI/VLSI digital memory and microprocessor circuits is based on the MOS Technology. More transistor and circuit functions can be achieved on a single chip with MOS technology, which is the considerable advantage of the same over bipolar circuits. Below given are the reasons for this advantage of MOS technology: Less chip area is demanded by an Individual…

Dielectric Isolation in Integrated Circuits This article focuses on Dielectric isolation in various Integrated Circuits; especially in the VLSI sector, discusses various methods used for dielectric isolation like V-groove isolation, Silicon on Insulator technology and Epitaxial layer overgrowth. Dielectric isolation, as you all know, is the process of electrically isolating various components in the IC chip from the substrate and from each other by an insulating layer. It’s main use is to eliminate undesirable parasitic junction capacitance or leakage currents associated with certain applications. The various methods of dielectric isolation are: V-Groove Isolation V-groove isolation is formed with an n-type…

The figure below shows some IC JFET structures. The n-channel JFET structure of first figure [a] is compatible with the n-p-n transistor fabrication sequence. Another view of this n-channel JFET is shown in second figure [a], where we note that the top p+ gate region extends beyond the n-type epitaxial layer region to make contact with the p-type substrate bottom gate. The n-type channel is thus completely encircled by the gate structure and the application of a suitably large negative voltage to the gate can pinch the channel off and reduce the drain-to-source current to essentially zero. If the p+…

Monolithic Planar Diode Configurations We have seen that in the fabrication of an IC the geometry and the doping of the various layers must be chosen to optimize uncharacteristic of the transistor which is the most important device. It is not economically feasible to provide extra processing steps to fabricate diodes. Therefore diodes are generally transistor adopted for this operation. There are basic five configurations of transistor for diode operation as shown in the figure below. A base-collector diode is shown in figure [a]. The emitter is floating and can be omitted. This diode has a high breakdown voltage  of…

Once all components are fabricated on a single crystal wafer, they must be electrically isolated from each other. The problem is not encountered indiscrete circuits, because physically all components are isolated. There are two methods of isolation in Integrated circuits. They are P-N  junction isolation and Dielectric isolation In this post we shall discuss p-n junction isolation. The method of isolation is most compatible with the IC processing, that is, one extra processing step, other than required to fabricate IC, is required in isolation. Basically the method involves producing islands of n- type material surrounded by p-type material. Components are…

In this post, we shall discuss, the fabrication of a standard, junction- isolated bipolar IC.  Of course, many devices can be formed at a time over the surface of the water if appropriate patterns are provided. We shall show only one device, that is, a bipolar transistor as an example. The major steps in the IC bipolar process are listed in the diagram below. The starting material is a p-type single crystal silicon wafer having 5 to 20 ohm-cm resistivity and thickness of approximately several hundred micrometers. The diameter can be 50, 75, 100, 125, or 150 mm. The most…