CCP Modules in PIC 16F877
TAKE A LOOK : INTRODUCTION TO PIC 16F877
TAKE A LOOK : PIC 16F877 – ARCHITECTURE AND MEMORY ORGANIZATION
TAKE A LOOK : REGISTER MEMORY ORGANIZATION IN PIC 16F877
TAKE A LOOK : TIMER MODULES IN PIC 16F877
CAPTURE/COMPARE/PWM (CCP) Modules in PIC 16F877
Capture-Compare-Pulse-Width-Module (CCP) is a special module designs for modulation and waveform generation applications. This module basically works on three different modes (capture/compare and PWM odes). The PIC 16F877 chip contains two CCP ports (CCP1 and CCP2). Each of this CCP module contains 16 bit registers which works as
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle registers
The CCP1 and CCP2 modules are identical in its operation except in its special event trigger operation. In each CCP modules, the capture, compare and PWM modes using different timer resources. The table below shows the different CCP modes and its timer resources. The detailed explanations and functions of CCP module is given below.
Capture/Compare/PWM Register 1 (CCPR1) is a 16 bit register comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1.
Capture/Compare/PWM Register 2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is generated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled).
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1.
An event is defined as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The type of event is configured by control bits, CCP1M3:CCP1M0 (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF (PIR1<2>), is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new value. The block diagram of capture mode is shown below.
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. The compare mode block diagram is shown below.
PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Figure shows a simplified block diagram of the CCP module in PWM mode.
Setup for PWM Operation
The following steps should be taken when configuring the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
The table below shows PWM FREQUENCIES and RESOLUTIONS AT 20 MHz and registers associated with CCP timer1/2 modules.
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