Design a PLL
Design for determining the Free running frequency,Lock range and Capture range of a PLL
In the earlier post about Phase Locked Loop IC we had discussed about the free-running frequency (fOUT), lock range (fL) and capture range (fc) equations. Here let us discuss about the appropriate values that can be given for fOUT, fL, and fc.
Given below is the circuit of an NE/SE 565 IC or the PLL IC.
We assume values for each parameter.
+V = 12 Volt
-V = -12 Volt
R1 = 15 Kilo Ohms
C1 = 0.01 Micro Farads
C2 = 10 Micro Farads
Free-running Frequency = 1.2 / 4R1 C1= 1.2 / (4*15*103* 0.01* 10-6) = 2 Kilo Hertz
Lock Range, fL = ± 8fOUT / V Hertz = 8*2*103/ +12 –(-12) = ±2/3 Kilo Hertz
Capture Range, fC = ± [fL / 2∏ (3.6) (10)3 C2]1/2 = [fL / 2∏*3.6*103*C2]1/2 = ±54.29 Hertz
From the above calculations, the relationship between free-running frequency, lock range and capture range are illustrated in the figure given below.
Block Diagram of NE SE565 PLL
Design of PLL
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Sir,
Is there any cheaper substitute of 565 is available. 565 is pricey, getting obsolete and less available day by day.
My intention is to design a FM/PM receiver.
pls I need a detailed circuit diagram of PLL including how to design each unit (phase detector, Filter and VCO,) with its explanations and relevant graphs. Its for my !st Degree Project
jelaia da zakupia integralna sxema 565 molia pichete na Email