As already mentioned in Field Effect Transistors (FET) , JFET’s are of two types, namely N-channel JFETs and P-channel JFETs. Generally N-channel JFETs are more preferred than P-channel. N-channel and P-channel JFETs are shown in the figures below.
The structure is quite simple. In an N-channel JFET an N-type silicon bar, referred to as the channel, has two smaller pieces of P-type silicon material diffused on the opposite sides of its middle part, forming P-N junctions, as illustrated in figure. The two P-N junctions forming diodes or gates are connected internally and a common terminal, called the gate terminal, is brought out. Ohmic contacts (direct electrical connections) are made at the two ends of the channel—one lead is called the Source terminal S and the other Drain terminal D.
The silicon bar behaves like a resistor between its two terminals D and S. The gate terminal is analogous to the base of an ordinary transistor(BJT). It is used to control the flow of current from source to drain. Thus, source and drain terminals are analogous to emitter and collector terminals respectively of a BJT.
In the figure above, the gate is P-region, while the source and the drain are N-regions. Because of this, a JFET is similar to two diodes. The gate and the source form one of the diodes, and the drain form the other diode. These two diodes are usually referred as the gate-source diode and the gate-drain diode. Since JFET is a silicon device, it takes only 0.7 volts for forward bias to get significant current in either diode.
With the gate terminal not connected, and a potential applied (+ ve at the drain and – ve at the source), a current called the drain current, ID flows through the channel located between the two P-regions. This current consists of only majority carriers-electrons in this case. P-channel JFET is similar in construction to N-channel JFET except that P-type semiconductor material is sandwiched between two N-type junctions, as shown in figure. In this case majority carriers are holes.
Standard Notations in FET:
Source – The terminal through which the majority carriers enter the channel, is called the source terminal S and the conventional current entering the channel at S is designated as Ig.
Drain – The terminal, througih which the majority carriers leave the channel, is called the drain terminal D and the conventional current leaving the channel at D is designated as ID.
The drain-to-source voltage is called VDS, and is positive if D is more positive than source S
Gate – There are two internally connected heavily doped impurity regions formed by alloying, by diffusion, or by any other method available to create two P-N junctions. These impurity regions are called the gate G. A voltage VGS is applied between the gate and source in the direction to reverse-bias the P-N junction. Conventional current entering the channel at G is designated as IG.
Channel – The region between the source and drain, sandwiched between the two gates is called the channel and the majority carriers move from source to drain through this channel.
Schematic Symbols of JFET
The schematic symbols for N-type and P-type JFETs are shown in the figure below. The vertical line in the symbol may be thought as channel and source S and drain D connected to the line.
Note that the direction of the arrow at the gate indicates the direction in which the gate current flows when the gate junction is forward biased. Thus for the N-channel JFET, the arrow at the gate junction points into the device and in P-channel JFET, it is away from the device.
The polarities for N-channel and P-channel JFET’s are shown in figures. In both of the cases the voltage between the gate and source is such that the gate is reverse biased. This is the normal method of connection of JFET’s. The drain and source terminals are interchangeable, that is either end can be used as a source and the other end as a drain. The source terminal is always connected to that end of the drain voltage supply which provides the necessary charge carriers, that is, in an N-channel JFET source terminal, S is connected to the negative end of the drain voltage supply for obtaining.
Operation of JFET
Let us consider an N-channel JFET for discussing its operation.
1. When neither any bias is applied to the gate (i.e. when VGS = 0) nor any voltage to the drain w.r.t. source (i.e. when VDS = 0), the depletion regions around the P-N junctions , are of equal thickness and symmetrical.
2. When positive voltage is applied to the drain terminal D w.r.t. source terminal S without connecting gate terminal G to supply, as illustrated in fig. 9.4, the electrons (which are the majority carriers) flow from terminal S to terminal D whereas conventional drain current ID flows through the channel from D to S. Due to flow of this current, there is uniform voltage drop across the channel resistance as we move from terminal D to terminal S. This voltage drop reverse biases the diode. The gate is more “negative” with respect to those points in the channel which are nearer to D than to S. Hence, depletion layers penetrate more deeply into the channel at points lying closer to D than to S. Thus wedge-shaped depletion regions are formed, as shown in figure. when Vds is applied. The size of the depletion layer formed determines–the width of the channel and hence the magnitude of current ID flowing through the channel.
To see how the width of the channel varies with the variation in gate voltage, let us assume that the gate is negative biased with respect to the source while the drain is applied with positive bias with respect to the source. This is shown in the figure above. The P-N junctions are then reverse biased and depletion regions are formed. P regions are heavily doped compared to the N-channel, so the depletion regions penetrate deeply into the channel. Since a depletion region is a regions depleted of the charge carriers, it behaves as an insulator. The result is that the channel is narrowed, the resistance is increased and drain current ID is reduced. If the negative voltage at the gate is again increased, depletion layers meet at the centre and the drain current s cut-off completely. If the negative bias to the gate is reduced, the width of the depletion layers gets reduced causing decrease in resistance and , therefore, increase in drain current ID.(The gate-source voltage VGS at which drain current ID is cut-off completely (pinched off) is called the pinch-off voltage Vp. It is also to be noted that the amount of reverse bias is not the same throughout the length of the P-N junction. When the drain current flows through the channel, there is a voltage drop along its length. The result is that the reverse bias at the drain end is more than that at the source end making the width of depletion layer more at the drain. To see how the width of the channel varies with the variation in gate, go through the figure above.