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TAKE A LOOK : IC FABRICATION TECHNIQUES
TAKE A LOOK : SILICON SUBSTRATE PREPARATION
TAKE A LOOK : CHEMICAL VAPOUR DEPOSITION (CVD)
Utility of Thermal Oxidation
The function of a layer of silicon dioxide (SiO2) on a chip is multipurpose. SiO2 plays an important role in IC technology because no other semiconductor material has a native oxide which is able to achieve all the properties of SiO2. The role of SiO2 in IC fabrication is as below :
It acts as a diffusion mask permitting selective diffusions into silicon wafer through the window etched into oxide.
- It is used for surface passivation which is nothing but creating protective SiO2 layer on the wafer surface. It protects the junction from moisture and other atmospheric contaminants.
- It serves as an insulator on the water surface. Its high relative dielectric constant, which enables metal line to pass over the active silicon regions.
- SiO2 acts as the active gate electrode in MOS device structure.
- It is used to isolate one device from another.
- It provides electrical isolation of multilevel metallization used in VLSI.
It is fortunate that silicon has an easily formed protective oxide, for otherwise we should have to depend upon deposited insulators for surface protection. Since SiO2 produces a stable layer, this has held back germanium IC technology.
Growth and Properties of Oxide Layers on Silicon
Silicon dioxide (silica) layer is formed on the surface of a silicon wafer by thermal oxidation at high temperatures in a stream of oxygen.
Si+02 = SiO2 (solid)
The oxidation furnace used for this reaction is similar to the diffusion furnace. The thickness of the oxide layer depends on the temperature of the furnace, the length of time that the wafers are in it, and the flow rate of oxygen. The rate of oxidation can be significantly increased by adding water vapour to the oxygen supply to the oxidizing furnace.
Si + 2H2O = SiO2 + 2H2
The time and temperature required to produce a particular layer thickness arc obtained from empirically determined design curves, of the type shown in the figures given below corresponding to dry- oxygen atmosphere and also corresponding to steam atmosphere.
In the past, steam was obtained by boiling ultra-high-purity water and passing it into the high-temperature furnace containing the silicon wafers; however, present day technologies generally use hydrogen and oxygen which are ignited in the furnace tube to form the ultra high-purify water vapour.
The process of silicon oxidation takes place many times during the fabrication of an IC. Once silicon has been oxidized the further growth of oxide is controlled by the thickness of the initial or existing oxide layer.
Growth Rate of Silicon Oxide Layer
The initial growth of the oxide is limited by the rate at which the chemical reaction takes place. After the first 100 to 300 A of oxide has been produced, the growth rate of the oxide layer will be limited principally by the rate of diffusion of the oxidant (02 or H20) through the oxide layer, as shown in the figures given below.
The rate of diffusion of O2 or H2O through the oxide layer will be inversely proportional to the thickness of the layer, so that we will have that
dx/dt = C/x
where x is the oxide thickness and C is a constant of proportionality. Rearranging this equation gives
xdx = Cdt
Integrating this equation both sides yields, x2/2 = Ct
Solving for the oxide thickness x gives, x = √2Ct
We see that after an initial reaction-rate limited linear growth phase the oxide growth will become diffusion-rate limited with the oxide thickness increasing as the square root of the growth time. This is also shown in the figure below.
The rate of oxide growth using H2O as the oxidant will be about four times faster than the rate obtained with O2. This is due to the fact that the H2O molecule is about one-half the size of the O2 molecule, so that the rate of diffusion of H2O through the SiO2 layer will be much greater than the O2 diffusion rate.
The interlace between silicon and silicon dioxide contains a transition region. Various charges are associated with the oxidised silicon, some of which are related to the transition region. A charge at the interface can induce a charge of the opposite polarity in the underlying silicon, thereby affecting the ideal characteristics of the MOS device. This results in both yield and reliability problems. The figure below shows general types of charges.
- Interface-trapped charges
These charges at Si-SiO2 are thought to result from several sources including structural defects related to the oxidation process, metallic impurities, or bond breaking processes. The density of these charges is usually expressed in terms of unit area and energy in the silicon band gap.
- Fixed oxide charge
This charge (usually positive) is located in the oxide within approximately 30 A of the Si –SiO2 interface. Fixed oxide charge cannot be charged or discharged. From a processing point of view, fixed oxide charge is determined by both temperature and ambient conditions.
- Mobile ionic charge
This is attributed to alkali ions such as sodium, potassium, and lithium in the oxides as well as to negative ions and heavy metals. The alkali ions are mobile even at room temperature when electric fields are present.
- Oxide trapped charge
This charge may be positive or negative, due to holes or electrons trapped in the bulk of the oxide. This charge, associated with defects in the Si02, may result from ionizing radiation, avalanche injection.
Effect of Impurities on the Oxidation Rate
The following impurities affect the oxidation rate
- Group III and V elements
In addition damage to the silicon also affects oxidation rate. As wet oxidation occurs at a substantially greater rate than dry oxygen, any unintentional moisture accelerates the dry oxidation. High concentrations of sodium influence the oxidation rate by changing the bond structure in the oxide, thereby enhancing the diffusion and concentration of the oxygen molecules in the oxide.
During thermal oxidation process, an interface is formed, which separates the silicon from silicon dioxide. As oxidation proceeds, this interface advances into the silicon. A doping impurity, which is initially present in the silicon, will redistribute at the interface until its chemical potential is the same on each side of the interface. This redistribution may result in an abrupt change in impurity concentration across the interface. The ratio of the equilibrium concentration of the impurity, that is, dopant in silicon to that in SiO2 at the interface is called the equilibrium segregation coefficient. The redistribution of the dopants at the interface influences the oxidation behaviour. If the dopant segregates into the oxide and remains there (such as Boron, in an oxidizing ambient), the bond structure in the silica weakens. This weakened structure permits an increased incorporation and diffusivity of the oxidizing species through the oxide thus enhancing the oxidation rate. Impurities that segregate into the oxide but then diffuse rapidly through it (such as aluminium, gallium, and indium) have no effect on the oxidation kinetics. Phosphorus impurity shows opposite effect to that of boron, that is, impurity segregation occurs in silicon rather than Si02. The same is true for As and Sb dopants.
Halogen (such as chlorine) impurities are intentionally introduced into the oxidation ambient to improve both the oxide and the underlying silicon properties. Oxide improvement occurs because there is a reduction in sodium ion contamination, increase in oxide breakdown strength, and a reduction in interface trap density. Traps arc energy levels in the forbidden energy gap which are associated with defects in the silicon.
Growth and Properties of Thin Oxides
MOS VLSI technology requires silicon dioxide thickness in the 50 to 500 A range in a repeatable manner. This section is devoted to the growth and properties of such thin oxide. This oxide must exhibit good electrical properties and provide long-term reliability. As an example, the dielectric material for MOS devices can be thin thermal oxide. This dielectric is an active component of the storage capacitor in dynamic RAMs, and its thickness determines the amount of charge that can be stored.
The growth of thin oxide must be slow enough to obtain uniformity and reproducibility. Various growth techniques for thin oxide are dry oxidation, dry oxidation with HCl, sequential oxidations using different temperatures and ambients, wet oxidation, reduced pressure techniques, and high pressure/low temperature oxidation. High pressure oxidation is discussed later. The oxidation rate will, of course, be lower at lower temperatures and at reduced pressures. Ultra-thin oxide (<50 A) have been produced using hot nitric acid, boiling water, and air at room temperatures. Some recent developments in thin oxide growth technique are
(i) Rapid thermal oxidation performed in a controlled oxygen ambient with heating provided by tungsten-halogen lamps and
(ii) Ultraviolet pulsed laser excitation in an oxygen environment.
The properties of thin oxide depend upon the growth technique employed. For example, oxide density increases as the oxidation temperature is reduced. Additionally, HCl ambients have typically been used to passivate ionic sodium, improve the breakdown voltage, and getter impurities and defects in the silicon. This passivation effect begins to occur only in the higher temperature range.
For thin oxides, there is an increase in leakage for a given voltage. In thin oxides the dielectric breakdown may be field-dependent (breakdown in a ramping field) or time-dependent (breakdown at a constant field). This breakdown is a failure mode for MOS ICs. Thinner oxides are more prone to failure.
High Pressure Oxidation
There is a benefit of increase in the oxidation rate if the thermal oxidation is carried out at pressures that are much above atmospheric pressure. The rate of diffusion of the oxidant molecules through an oxide layer is proportional to the ambient pressure. For example, at a pressure of 10 atm the diffusion rate will be increased by a factor of 10 and the corresponding oxidation time can be reduced by nearly the same factor. Alternatively, the oxidation can be done for the same length of time, but the temperature required will be substantially lower.
Thus, one principal benefit of high-pressure oxidation processing is lower-temperature processing. The lower processing temperature reduces the formation of crystalline defects and produces less effect on previous diffusions and other processes. The shorter oxidation time is also advantageous in increasing the system throughput. The major limitation of this process is the high initial cost of the system.
The oxide layer is used to mask an underlying silicon surface against a diffusion (or ion implantation) process. The oxide layer is patterned by the phtolithographic process to produce regions where there are opening or “windows” where the oxide has been removal to expose the underlying silicon. Then these exposed silicon regions are subjected to the diffusion (or implantation) of dopants, whereas the unexposed silicon regions will be protected. The pattern of dopant that will be deposited into the silicon will thus be a replication of the pattern of opening in the oxide layer. The replication is a key factor in the production of tiny electronic components.
The thickness of oxide needed for diffusion masking is a function of the type of diffusant and the diffusion time and temperature conditions. In particular, an oxide thickness of some 5000 A will he vufftcieni to mask against almost all diffusions. This oxide thickness will also be sufficient to block almost alt but the highest-energy ion implantation.
The other function of Si02 in IC fabrication is the surface passivation. This is nothing but creating protective Si02 layer on the wafer surface. The figure below shows a cross-sectional view of a p-n junction produced by diffusion through an oxide window. There are lateral diffusion effects, that is, the diffusion not only proceeds in the downward direction, but also sideways as well, since diffusion is an isotropic process. The distance from the edge of the oxide window to the junction in the lateral direction underneath die oxide is indicated as yj.