Description.

Here is the circuit diagram of a simple 100 watt inverter using IC CD4047 and MOSFET IRF540. The circuit is simple low cost and can be even assembled on a veroboard.

CD 4047 is a low power CMOS astable/monostable multivibrator IC. Here it is wired as an astable multivibrator producing two pulse  trains of 0.01s which are 180 degree out of phase at the pins 10 and 11 of the IC. Pin 10 is connected to the gate of Q1 and pin 11 is connected to the gate of Q2. Resistors R3 and R4 prevents the loading of the IC by the respective MOSFETs. When pin 10 is high Q1 conducts and  current flows through the upper half of the transformer primary which accounts for the positive half of the output AC voltage. When pin 11 is high Q2 conducts and  current flows through the lower half of the transformer primary in opposite direction and it accounts for the negative half of the output AC voltage.

Circuit diagram.

Notes.

• B1 can be  a 12V/ 6Ah lead acid battery.
• Q1 and Q2 must be fitted to a proper heat sink.
• T1 can be a 9-0-9 V primary, 230V secondary, 150VA transformer .
• Do not expect much from this circuit. The is very simple one suitable for low grade applications.

To know the basics, click on the links given below.

TAKE A LOOK : SHORT CHANNEL MOS STRUCTURES

TAKE A LOOK : V-GROOVE MOS (VMOS)

The V-groove MOS (VMOS) structure is another short-channel power FET constructed as a vertical structure. It operates exactly as the DMOS device. The figure below shows a VMOS structure. This is again a double-diffused device in which the channel length is set by the difference between the n⁺ and p-type diffusions.

The lightly doped -type epitaxial layer and the room allowed for the expansion of the depletion region between the p⁺ diffused layer and the n⁺ substrate will lead to a high breakdown voltage (BV_DS greater than or approximately equal to 50 V) and a low drain capacitance. At the same time the drain series resistance is kept to a small value as a result of the heavily doped n⁺ substrate. The wall of the V-shaped groove is covered by a SiO₂ insulation layer and then by an aluminium layer which serves as a gate. Since the p-region stretches as a channel above the substrate, it is easy to form a channel as short as 1micro meter, which is essential for high-speed MOSFETs, using conventional mask lithography, because the channel length (that is, the layer thickness) is independent of mask resolution.

One distinguishing feature of VMOS is the anisotropically-etched V-groove cut normally to the surface that extends through both the n⁺, p and penetrates slightly the epitaxial region. By virtue of this V-groove easy access is provided for the gate to overlay the p-diffusion which acts as the current conducting channel. Since the MOSFETs are formed on the slopes of the grooves, the packing density of such devices on a chip is high.

VMOS structure

The V-grooves are produced by an anisotropic or orientation – dependent etching (ODE) process. The etchant, such as KOH at 80 to 100°C, attacks silicon very rapidly in the [100] crystallographic direction, but very slowly in the [111] direction. For (100) oriented silicon substrates the result will be the production of V-shaped grooves that have (111) side walls as shown in the figure below. The angle of the (111) groove side walls with respect to the (100) silicon surface will be 54.74°. The width of the grooves, W, is controlled by the width of the opening in the oxide layer, which is used as an etching mask since SiO₂ is attacked only very slowly by the etching solution.

Isotropic-Anisotropic Etching

The gate of the VMOS transistor is formed on the (111) faces of pyramidal-shaped crater, and extends around the perimeter of the pyramidal area. As a result, the width of the channel is very large compared with its length. This large width to length ratio improves the transconductance of the device and is achieved on a very small area of the silicon chip. VMOS structures with large arrays of very many V-grooves gate structures are available with current ratings of up to several amperes.

VMOS applications include hi-fi audio power amplifiers, broadband high-frequency amplifiers, and also switching power amplifiers which converts  ac power sources into dc at arbitrary voltage, with lower cost, lighter weight, and smaller size than conventional power supplies.

Vertical DMOS structures consisting of a very large number of parallel connected cells in a rectangular or hexagonal pattern on a common n/n⁺ drain region are available with continuous current ratings in excess of 25 A at voltages of up to 500 V, which gives a  power handling capability of 12.5 kW. The very short channel length and very large total channel width that can be of the order of 1 million times greater than the channel length can also result in very small values for the drain-to-source on resistance.

To know the basics of DMOS take a look at the following posts.

TAKE A LOOK : SHORT CHANNEL MOS STRUCTURES

The figure below shows a double-diffused MOS (DMOS) structure. The channel length, L, underneath the gate oxide is the lateral distance between the n⁺ p junction and the p-n substrate junction, and is thus controlled by the junction depth produced by the n⁺ and p-type diffusions. This is similar to the situation with respect to the base width of a double-diffused bipolar transistor, and the channel length can be made to be as small as 0.5 micro meters. The application of a suitably large positive voltage to the gate [>V_TH] will invert the p-substrate region underneath the gate to n- type , and the resulting n-type surface inversion layer will serve as a conducting channel for the flow of electrons from source to drain.

DMOS Structure

The n-type substrate is lightly doped. This makes room available for the expansion of the depletion region between the p-type diffusion region and the n⁺ drain contact region. In turn, this will make-possible a relatively high breakdown voltage between drain and source [BV_DS].

Vertical DMOS Structure

The figure below shows a vertical DMOS structure. In this case the drain contact region is n⁺ substrate. The removal of the n drain contact regions from top surface will allow for more parallel-connected channels to be formed so that the transfer conductance and the drain current capability of the device can be correspondingly increased with a large high-density array of very many gate electrodes on the top surface, vertical DMOS devices with current ratings of up to 10 A are possible.

The double-diffused MOS structure as shown above was one of the earlier successful efforts in short-channel MOSFET technology. The name “DMOS” comes from the sequential manner in which the p- doped substrate diffusion is followed by highly doped n⁺ source diffusion. The short channel results from careful control and placement of the second (n⁺) diffusion. The DMOS process had undergone continual refinement so that it became one of major power FET technologies. When early high-voltage DMOS devices with lateral structures became unduly large, their advantages were soon offset by the traditional drawback of large geometries. Consequently, vertical structures were developed. There are two principal variations of vertical MOSFET structures. One variation is shown in the figure below. Another type of vertical MOS structure is discussed in the next post.

V-DMOS Transistor

All high-voltage, high power DMOS structures are constructed with the source and gate located on the top of the chip-and the drain on the underside, as shown in the figure above. VDMOS power FET’s can withstand extremely high voltages with device ratings approaching the kilovolt range. Operationally, there is little difference between the vertical structure and its planer or lateral equivalent. But VDMOS devices have a higher breakdown voltage, and smaller chip sizes resulting in higher yield.

To know about VMOS click on the link below.

TAKE A LOOK : V-GROOVE MOS (VMOS)

There are many factors that limit the speed of a MOSFET. Because of parasitic capacitances and resistances, channel current and consequently output voltage change slowly. This is due to the fact that when the input voltage at the gate input changes, parasitic capacitances must be charged or discharged through a parasitic resistance. The greater these parasitics are the slower the charging or discharging. The parasitic capacitances of diffusion regions against the gate and substrate namely, C_gd, C_gs, C_db and C_sb, have sufficient values. These parasitics can be reduced by the self-aligned gate structure.

The parasitics can also be reduced by scaling down of the dimensions. Some common methods are explained below.

1. Scaled MOS (SMOS)

The scale down of the dimensions of a MOSFET with a metal gate or a silicon gate, along with the appropriate adjustment of the parameters, also improves the speed and reduces power consumption because parasitic capacitances are reduced; In particular, reduction of channel length, that is, the length between drain and source increases the speed because the transit time of the earners to cross the channel is reduced, and the parasitic capacitances are also reduced.

Usually the channel length chosen is the minimum with which a MOSFET works properly. If it is too short, estimated to be about 0.2 micro meters, the MOSFET has complex physical phenomenon such as voltage breakdown, and punch through. The punch through causes current flow between source and drain without being controlled by the gate voltage. The minimum channel length in 1976 for depletion mode MOSFET was 6 micro meters which was brought down to 1.5 micro meters in 1982. This has reduced correspondingly the delay of a logic gate using MOS from 4 nano seconds to 0.2 micro seconds. It should be noted that for the sake of convenience, the horizontal length L’ of the silicon gate in the figure shown below is usually called channel length by the manufacturers because this length appears in a mask. In order to differentiate it from the real channel length L, this could be called a mask channel length. A scaled down n-MOS is usually called high-performance MOS (HMOS), as announced in 1977 by Intel and improved in later years.

SMOS and HMOS

A typical HMOS employs a single ion implantation to increase the doping level at the surface region of MOS to control the threshold voltage and increase the punch-through voltage. A double implanted HMOS as shown in the second figure above has p1 and p2 regions. The p1 region contains the threshold control implant, and the pt region contains the punch-through control implant. Using double implants, the HMOS with physically small-channel lengths can be tailored to minimise the effects occurring due to short channel. As the channel is shortened, departure from long- channel behaviour may occur as a result of a two dimensional potential distribution and high electric fields in the channel region.

The higher transfer conductance, in turn, leads to a larger voltage gain and gain-bandwidth product. Also, the drain current I_D at any given gate voltage will be larger, so that the current- handling capability of the device is increased. Indeed, current ratings of up to 10 A are available with some

VMOS and vertical DMOS devices as discussed in the following posts.

TAKE A LOOK : DOUBLE-DIFFUSED MOS (DMOS)

TAKE A LOOK : V-GROOVE MOS (VMOS)

There are a large number and variety of basic fabrication steps used in the production of modem MOS ICs. The process could be designed for NMOS or PMOS or CMOS devices. The gate could use metal or poly-silicon (as described in this section for NMOS device). The substrate could be bulk silicon or silicon-on-sapphire (SOS). Finally, there are variations in the techniques to isolate the devices in the wafer to avoid parasitic transistors..

This post describes the silicon-gate process. The important distinguishing characteristics of such structure will be described later.

The fabrication sequence of n-channel MOS IC is shown in the figure below.

1. A thin layer of Si₃N₄ is deposited on entire wafer surface by chemical vapour deposition (CVD).The first photolithographic step defines area where transistors are to be fabricated. The Si₃N₄ is removed outside the transistor areas by chemical etching. The impurity, boron, is implanted in the exposed regions to suppress unwanted conduction between transistor sites. Next, SiO₂ layer of about 1 micro meters thickness is grown in these inactive, or field regions by exposing the wafer to oxygen in an electric furnace. This is known as selective or local oxidation process. The Si₃N₄ is impervious to oxygen and thus inhibits growth of the thick oxide in the transistor regions.
2. Next, the Si₃N₄ is removed by an etchant that does not attack SiO₂. A layer of oxide about 0.1 micro meters thick is grown in the transistor areas. Then a layer of poly-Si is grown over entire wafer by CVD process. The second photolithographic step defines the desired patterns for gate electrodes. Undesired poly-Si is removed by chemical or plasma etching. An n-type dopant, such as phosphorus or arsenic, is introduced into the regions that will become the source and drain of MOS device. For this, diffusion or ion implantation is used. The thick field oxide and the poly- silicon gate are barriers to the dopant, but in this process, the poly-Si becomes heavily n-type.
3. Again, an insulating layer, SiO₂, is deposited by CVD process. The third photolithographic step defines the areas in which contacts to the transistors are to be made, as shown in the figure given above. Chemical or plasma etching selectively exposes bare silicon or poly-Si in the contact areas.
4. For interconnection, Al is used. The fourth masking step patterns the Al as desired for circuit connections as indicated in the figure given above.

The final steps of the process are identical to those described for bipolar transistor ICs. Above process is the simplest possible. For advanced processing of NMOS and CMOS, 7 to 12 masking steps are required.