Phase Locked Loop IC’s
MONOLITHIC PHASE-LOCKED LOOP (PLL) ICS
Although the evolution of the PLL began in the early 1930s but its cost outweighted its advantage in the beginning. Today the PLL is even available as a single package, typical examples of which are the Signetic’s SE/NE series such as 560, 561, 562, 564, 565 and 567. They only differ in operating frequency range, power requirements, and frequency and bandwidth (BW) adjustment ranges. SE/NE 565 is the most widely employed IC of the series. The device is available as a 14-pin DIP package and as a 10-pin metal can package. Its important electrical characteristics are given below:
Characteristics of SE/NE 565 PLL IC
- Operating frequency range : 0.001 Hz to 500 kHz.
- Operating voltage range : ± 6 to ± 12 V.
- Input impedance : 10 k Q typically.
- Output sink current :1mA typically.
- Output source current : 10 m A typically.
- Drift in VCO centre frequency with temperature : 300 ppm/ °C typically.
- Drift in VCO centre frequency with supply voltage : 1.5 %/V maximum.
- Input level required for tracking : 10 mVrms minimum to 3 V peak-to-peak maximum.
- Bandwidth adjustment range : < ± 1 to > ± 60 %.
The block diagram and connection diagram of the SE/NE 565 IC is shown in figure. As shown in the figure, the PLL system consists of a phase detector or comparator (PC), a voltage-controlled oscillator (VCO), an amplifier and R-C combination forming low-pass filter circuit. The input signals are fed to the phase detector through pins 2 and 3 in differential mode. The input signals can be direct-coupled provided that the dc level at these two pins is made same and dc resistances seen from pins 2 and 3 are equal. By shorting pins 4 and 5 output of VCO is supplied back to the phase comparator (PC). The output of PC is ijiternally connected to amplifier, the output of which is available at pins 6 and 7 through a resistor of 3.6 k Q connected internally. A capacitor C2 connected between pins 7 and 10 forms a low-pass filter with 3.6 k Q resistor. The filter capacitor C2 should be large enough so as to eliminate the variations in demodulated output and stabilize the VCO frequency. Voltage available at pin 7 is connected internally to VCO as a control signal. At pin 6 a reference voltage nominally equal to voltage at pin 7 is available allowing both the differential stages to be biased. Pins 1 and 10 are supply pins.
The centre frequency of the PLL is determined by the free-running frequency of the VCO which is given as
Fout = 1.2/4R1C1 Hertz
where R1 and C1 are external resistor and capacitor connected to pins 8 and 9 respectively, as illustrated in figure. The free-running frequency fout of the VCO is adjusted, externally with Rt and C1, to be at the centre of the input frequency range. Resistor R1 must have a value between 2 and 20 kilo ohm. Capacitor C1 may have any value.
The 565 PLL can lock to and track an input signal typically ± 60 % bandwidth with respect to fout as the centre frequency. The lock-range of PLL is given as
fL = ± 8fOUT / V Hertz
where fout is free-running frequency of VCO in Hz and V = (+ V) – (- V) and capture range is given as
fC = ± [fL / 2∏ (3.6) (10)3 C2]1/2
The lock range usually increases with an increase in input voltage but falls with an increase in supply voltages.