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Operating principle of Phase Locked Loops

Phase Locked Loop

The block diagram showing operating principle of PLL is given in figure. As illustrated in this fig, the PLL consists of a phase detector, a low-pass filter and a voltage controlled oscillator.

Phase Detector

A phase detector is basically a comparator that compares the input frequency f_in with feedback frequency f_out. The phase detector receives two digital signals, one from the input, the other feedback from the output. The loop is locked when these two signals are of the same frequency and have a fixed phase difference (A locked PLL is analogous to an op-amp not being saturated). The output of a phase detector is a dc voltage and therefore is often referred to as the error voltage, V_e. DC output voltage becomes maximum when the phase difference between the two frequencies f_in and f_out is ∏ radians or 180°. Without input signal, the error voltage V_e is equal to zero and the VCO operates at a set frequency ‘f_r‘ which is also called free-running frequency of the VCO. When the input signal frequency is the same as that from the VCO to the PC, the voltage, V_d, taken as output is the value required to hold the VCO in lock with the input signal. If the two input pulses to the PC are of exactly the same frequency and phase, the output of the PC is zero, otherwise there I will be an output proportional to their phase difference.

Low-pass filter

Low-pass filter is used to remove high frequency components and noise from the output of the phase detector. It affects the dynamic characteristics of the PLL including bandwidth, capture and lock ranges and transient response. The low-pass filter accepts the output from the phase detector, removes the high frequency noise and produces a dc level.

Voltage Controlled Oscillator (VCO)

Voltage-controlled oscillator generates frequency controlled by input voltage. The dc level output of a low-pass filter is applied as control signal to the voltage-controlled oscil­lator (VCO). The output frequency of the VCO is directly proportional to the input dc level. The VCO frequency is adjusted till it becomes equal to the frequency of the input signal. During this adjustment, PLL goes through three stages-free running, capture and phase lock. Best operation is obtained if the centre frequency of the VCO is set with the dc bias voltage midway in its linear operating range. The amplifier allows this adjustment in dc voltage from that obtained as output of the filter circuit. When the loop is in lock, the two signals to the PC are necessarily of the same frequency although not necessarily in phase. A fixed phase difference between the two signals to the comparator results in a fixed dc voltage to the VCO. Variation in the input signal frequency then causes variation in the dc voltage to the VCO. Within a capture-and-Iock frequency range, the dc voltage will drive the VCO frequency to match that of the input.

While the loop is trying to achieve lock, the output of the PC contains frequency components at the sum and difference of the signals compared. A low-pass filter passes only the lower-frequency component of the signal so that the loop can obtain lock between input and VCO signals.

Owing to the limited operating range of the VCO and the feedback connection of the PLL circuit, there are two important frequency bands specified for a PLL. The capture range of a PLL is the range of frequencies centred about the VCO free-running frequency f_r, over which the output signal frequency of the VCO can acquire lock with the input signal frequency. Once the PLL has achieved capture, it can maintain lock with the input signal over a somewhat wider frequency range called the lock range.