How a PLL works ?

PLL Operation

Consider VCO operating without input signal at free-running frequency f_r and input signal of frequency f_IN increasing from zero is applied to the PC. If the input frequency is less than f_IN1, then the error voltage V_e is zero as illustrated in figure and VCO operates at a frequency f_r. When the input signal frequency f_IN reaches a frequency f_in1 (the lower edge of the capture range), then the output or error voltage V_e jumps from zero to some negative voltage with beat notes of frequency (difference between input signal frequency and actual VCO output signal frequency; f_IN – f_OUT. The error voltage V_g is then filtered, amplified and amplified voltage V_d is applied to the control terminals of the VCO. The instantaneous frequency of VCO decreases because f_OUT falls for nega­tive values of V_d and increases for positive values of V_rf. At some instant of time, the decreasing frequency of the VCO equals f_{IN l} (lower edge of the capture range), then lock results-in, and the output signal frequency of the

VCO may be equal to the input signal frequency (that is,f_OUT = f_IN). The VCO frequency locks with input signal frequency up to f_IN2 (the upper end of the lock range). If the input signal frequency exceeds f_IN2 then error voltage V_g will fall to zero and the VCO will operate at the free running frequency f_r, as illustrated in figure. If the input signal frequency is now slowly swept back and it attains the value of f_d1 then the loop (VCO frequency) locks with the input signal frequency, causing a positive jump of the error voltage V_e. So the VCO output frequency increases from f_r continuously till f_OUT becomes equal to f_IN. The VCO frequency f_OUT locks with the input signal frequency f_IN upto f_d2 (the lower edge of the lock range) as shown in figure by dotted lines. Now if the frequency of the input signal falls below f_d2, then the error voltage V_e will fall to zero and the VCO will operate at the free running frequency.