Introduction to PLL or Phase Locked Loops

Phase-locked loop is a feedback loop consisting of a phase detector, a low-pass filter, amplifier (optional) and a voltage-controlled oscillator (VCO), as illustrated in figure. It plays the same role in the frequency or phase world as the op-amp does in the voltage world. The op-amp has two voltage inputs, non-inverting and inverting (normally used for feedback from the output). Similarly, the PLL has two inputs; the PLL’s feedback input is normally connected to the circuits’ output. Digital frequencies are usually applied. The op-amp changes its output voltage to whatever values is necessary to drive the difference in voltage between its two inputs to zero. The PLL changes its output phase and frequency to whatever frequency or phase is necessary to make the two input frequencies and phase track. Placing a voltage divider in the feedback loop of an op-amp causes the output voltage to be increased by the amount of the feedback voltage division (amplification). Placing a frequency divider in the feedback of a PLL causes the output frequency to be increased by the amount of the feedback divider. A firm grasp on similarities between the PLL and the op-amp simplifies our analysis and design of circuits containing PLLs.

Phase Locked Loop

With the rapid development of IC technology, the phase-locked loop (PLL) has emerged as one of the fundamental building blocks in electronic technology.

Common applications of a PLL include

(i) frequency synthesizers that provide multiples of a reference signal fre­quency;

(ii) FM demodulation networks for FM operation with excellent linearity between the input signal frequency and the PLL output voltage;

(iii) demodulation of the two data trans­mission or carrier frequencies in digital-data transmission employed in frequency-shift keying (FSK) operation;

(iv) a wide variety of areas including telemetry receivers and transmit­ters, tone decoders, AM detectors, tracking filters and motor speed controls.

OTHER PLL RELATED POSTS:

PLL Operating Principle

Phase Locked Loop IC’s

PLL Design for Lock Range and Capture Range

How a PLL Works ?

PLL Application:Frequency Multiplication

PLL Application: Frequency Demodulation

PLL Application:FSK Demodulator

Programmable UJT

The programmable unijunction transistor (PUT) is not a unijunction transistor at all. The fact that the V-I characteristics and applications of both are similar prompted the choice of labels.

It is also a four-layer P-N-P-N solid-state device with a gate connected directly to the sandwiched N-type layer. The basic structure, schematic symbol and the basic biasing arrangement of PUT are shown in figures respectively. As the symbol indicates, it is essentially an SCR with a control mechanism that permits a duplication of the characteristics of the typical SCR. The term “programmable” is applied because the inter base resistance R_BB, the intrinsic stand-off ratio Ƞ and peak-point voltage V_P, as defined in UJT can be programmed to any desired values through external resistors R_B and R_B2 and the supply voltage V_BB. From figure we see that by voltage divider rule when I_G = 0,

V_G =   (R_B1 / R_B1 + R_B2 )  V_BB =  Ƞ  V_BB

Consider figure The P-N-P-N device shown in figure has its gate connected to the junction of external resistors R_B and R_B . The four-layer construction shown in figure indicates that the anode-gate junction is forward biased when the anode becomes positive with respect to gate. When this occurs, the device is turned on. The anode-to-cathode voltage V_AK then drops to a low level, and the device conducts heavily until the input voltage become too low to sustain conduction. It is seen that this action stimulates the performance of a UJT. The anode of the device acts as the emitter of UJT.

Characteristics of Programmable UJT

The typical characteristics of the device are shown in figure. The firing or peak-point potential is given as

V_P = Ƞ V_BB + V_{B  as defined for the UJT.}

However V_P represents the voltage drop V_AK in figure [ the forward voltage drop across the conduct­ing diode]. For silicon V_B is typically 0.7 V.

In PUT R_B1 and R_B2 are the external resistors to the device permitting the adjustment of Ƞ and hence V_G while in the UJT both R_B1 and R_B2 represent the bulk resistance and ohmic base contacts of the device (both inaccessible).  Although the characteristics of the PUT and UJT are similar, the peak and valley currents of the PUT are typically lower than those of a UJT of a similar rating. In addition, the minimum operating voltage of PUT is also lower than that of UJT.

Application of PUT

PUT RElaxation Oscillator

PUT, because of its superiority over UJT, replaces UJT. One popular application of PUT is in the relaxation oscillator shown in figure. The instant the supply V_BB is switched on, the capacitor starts charging toward V_BB volts, since there is no anode current at this point. The instant the voltage across the capacitor equals V_P, the device fires and anode current I_A = I_P is established through the PUT. As soon as the device fires, the capacitor starts discharging rapidly through the low on-resistance of the PUT and R_K. Consequently, a voltage spike is produced across R_K during the discharge. As soon as the capacitor C gets discharged, the PUT turns off and the charging cycle starts all over again as narrated above.

The time period required to attain the firing potential V_P is given approximately by the expression

T = RC log_e = V_BB / V_BB – V_P = Ƞ V_BB

At the point of firing of PUT
I_P R = V_BB – V_P

If R is too large, the current I_P cannot be established, and the device will not fire

So R_MAX = V_BB – V_P / I_P

Similarly  R_MIN = V_BB – V_V / I_V

V_BB – V_P / I_P > R > V_BB – V_V / I_V

UJT Relaxation Oscillator

The relaxation oscillator shown in figure consists of UJT and a capacitor C which is charged through resistor R_E when inter base voltage V_BB is switched on. During the charging period, the voltage across the capacitor increases exponentially until it attains the peak point voltage V_P. When the capacitor voltage attains voltage V_P, the UJT switches on and the capacitor C rapidly discharges through B_1. The resulting current through the external resistor R develops a voltage spike, as illustrated in figure and the capacitor voltage drops to the value V_V. The device then cuts off and the capacitor commences charging again. The cycle is repeated continually generating a saw-tooth waveform across capacitor C. The resulting waveforms of capacitor voltage V_C and the voltage across resis­tor R (V_R) are shown in figure. The frequency of the input saw-tooth wave can be varied by varying the value of resistor R_E as it controls the time constant (T = R_EC) of the capacitor charging circuit. The discharge time t₂ is difficult to calculate because the UJT is in its negative resistance region and its resistance is continually changing. However, t₂ is normally very much less than t₁ and can be neglected for approximation.

For satisfactory operation of the above oscillator the following two conditions for the turn-on and turn-off of the UJT must be met.

R_E < V_BB – V_P / I_P and R_E > V_BB – V_V / I_V

That is the range of resistor R_E should be as given below

V_BB – V_P / I_P > R_E >  V_BB – V_V / I_V

The time period and, therefore, frequency of oscillation can be derived as below. During charging of capacitor, the voltage across the capacitor is given as

V_c = V_BB(l-e^-t/ReC)

where R_EC is the time constant of the capacitor charging circuit and t is the time from the commencement of the charging.The discharge of the capacitor commences at the end of charging period t₁ when the voltage across the capacitor V_c becomes equal to V_P, that is, (Ƞ V_BB + V_B)

V_P = Ƞ V_BB + V_B = V_BB(l-e^-t/ReC)

Neglecting V_B in comparison to Ƞ V_BB we have

Ƞ V_BB = V_BB(l-e^-t1/ReC)

or   e^-t1/ReC = 1 – Ƞ

So charging time period, t₁ = 2.3 R_E C log₁₀ 1/1- Ƞ

Since discharging time duration t₂ is negligibly small as compared to charging time duration t₁ so taking time period of the wave, T = t₁

Time period of the saw-tooth wave, T = 2.3 R_E C log₁₀ 1/1- Ƞ

and frequency of oscillation f = 1/T = 1/2.3R_EClog₁₀ (1-Ƞ)

By including a small resistor in each base circuit, three useful outputs (saw-tooth waves, positive triggers, and negative triggers), as shown in   figure, can be obtained. When the UJT fires, the surge of current through B_t causes a voltage drop across R₁ and produces the positive going spikes. Also at the UJT firing time, the fall of V_EB causes I_B to rise rapidly and generate the negative-go­ing spikes across R₂, as shown in figure. R₁ and R₂ should be much smaller than R_BB to avoid altering the firing volt­age of the UJT. A wide range of oscillation fre­quencies can be achieved by making R_E adjustable and including a switch to select different values of capacitance, as illustrated. As already mentioned in previous blog post there is upper and lower limits to the signal source resistance R_E for the satisfactory operation of the UJT.

How to trigger an SCR using UJT ?

UJT Triggering

One common application of the uni junction transistor is the triggering of the other devices such as the SCR, triac etc. The basic elements of such a triggering circuit are shown in figure. The resistor R_E is chosen so that the load line determined by R_E passes through the device characteristic in the negative resistance region, that is, to the right of the peak point but to the left of the valley point, as shown in figure. If the load line does not pass to the right of the peak point P, the device cannot turn on.

For ensuring turn-on of UJT

R_E <    V_BB – V_p­ / I_P

This can be established as below

Consider the peak point at which I_RE = I_p and V_E = V_P

(the equality I_RE = I_P is valid because the charging current of capacitor, at this instant is zero, that is, the capacitor, at this particular instant, is changing from a charging state to

a discharging state). Then V_E = V_BB – I_RE R_E

So, R_E(MAX) =  V_BB – V_E­ / I_RE = V_BB – V_p­ / I_P at the peak point.

At the valley point, V

I_E = I_V and V_E = V_V so that

V_E = V_BB – I_RE R_E

So R_E(MIN) = V_BB – V_E / I_RE = V_BB – V_V / I_V or for ensuring turn-off.

R_E > = V_BB – V_V / I_V

So, the range of resistor R_E is given as

V_BB – V_P / I_P >R_E > V_BB – V_V / I_V

The resistor R is chosen small enough so as to ensure that SCR is not turned on by voltage V_R when emitter terminal E is open or I_E = 0

The voltage V_R = RV_BB/R + R_BB for open-emitter terminal.

The capacitor C determines the time interval between triggering pulses and the time duration of each pulse. By varying R_E, we can change the time constant R_E C and alter the point at which the UJT fires. This allows us to control the conduction angle of the SCR, which means the control of load current.

Current ratings of an SCR

The current carrying capability of an SCR is solely determined by the junction temperature. Except in case of surge currents, in no other case the junction temperature is permitted to exceed the permissible value. Some of the current ratings used in industry to specify the device are given below.

(i) Forward Current Rating.

The maximum value of anode current, that an SCR can handle safely (without any damage), is called the forward current rating. The usual current rating of SCRs is from about 30 A to 100 A. In case the current exceeds the forward current rating, the SCR may get damaged due to intensive heating at the junctions.

(ii) On-state Current.

When the device is in conduction, it carries a load current determined by the supply voltage and the load. On-state current is defined in terms of average and rms values.

I_Tav is the average value of maximum continuous sinusoidal on-state current (frequency 40-60 Hz, conduction angle 180°) which should not be exceeded even with intensive cooling. The temperature at which the current is permissible has to be mentioned. It is this current which determines the application of device.

I_Trms is the rms value of maximum continuous sinusoidal on-state current (frequency 40-60 Hz, conduction angle 180°) which should not be exceeded even with intensive cooling.

Latching Current.

It is the minimum device current, which must be attained by the device, before the gate drive is removed while turning-on, for maintaining it into conduc­tion.

Holding Current.

It is the minimum on-state current required to keep the SCR in conducting state without any gate drive. Its usual value is 5 m A.

(v) Surge Current.

It is the maximum admissible peak value of a sinusoidal half cycle of 10 ms duration at a frequency of 50 Hz. The value is specified at a given junction temperature.

During maximum surge on-state current the junction temperature is exceeded though temporarily and forward blocking capabilities are lost for a short period. The maximum surge on-state current should only occur occasionally.

(vi) I²t Value.

I²t value is the time integral of the square of the maximum sinusiodal on-state current. This is usually specified for 3 ms and 10 ms, and determines the thermal rating of the   device.

(vii) Critical Rate of Rise of Current.

The maximum rate of increase of current during on-state which the SCR can tolerate is called the critical rate of rise of current for the device. This is specified at maximum junction temperature.

During initial period of turning-on, only a small area near the gate conducts the anode current. If the current increases too fast, localised overheating may take place. This is called the hole storage effect. Due to localised heating the device may get permanently damaged. To-day devices are available which can withstand rate of rise of current upto 200-250 A/microsecond, however in application this rate is hardly allowed to exceed beyond 5-10 A/micro second.

Protection against dI/dt is provided by series inductor.