Power MOSFETs are usually constructed in V-configuration, as shown in figure. That is why, the device is sometimes called the V-MOSFET or V-FET. V-shaped cut penetrates from the device surface almost to the N+ substrate through N+, P and N~ layers, as seen from figure. The N+ layers are heavily doped, low resistive material, while the N~ layer is a lightly doped, high-resistance region. The silicon dioxide dielectric layer covers both the horizontal surface and V-cut surface. The insulated gate is metal film deposited on the Si02 in the V-cut. Source terminals make contact to the upper N+ and P-layers through the Si02 layer. The N+ substrate is the drain terminal of the device.
V-MOSFET is an E-mode FET and no channel exists between drain and source until the gate is positive with respect to the source.On making gate positive with respect to the source, an N-type channel is formed close to the gate, as in the case of an E-MOSFET. In this case, N-type channel provides a vertical path for the charge carriers to flow between the N+ substrate (i.e. drain) and the N+ source termination. When VGS is zero or negative, no channel exists and the drain current is zero.
The drain and transfer characteristics for the enhancement-mode N-channel power MOSFET are similar to those for the E-MOSFET, as illustrated in figs. With the increase in gateÂ voltage, the channel resistance is reduced and, therefore, the drain current ID increases. Thus the drain current ID can be controlled by gate voltage control so that for a given level of VGS, ID remains fairly constant over a wide range of VDS levels.
Drain terminal being at the bottom of the V-MOSFET (instead of at the top surface) can have a considerable large area for any given size of the device. This allows much greater power dissipation than are possible in a MOSFET having both drain and source at the surface.
In the power or V-MOSFETs the channel length is determined by the diffusion process, while in other MOSFETs the channel length depends upon the dimensions of the photographic masks employed in the diffusion process. By controlling the doping density and the diffusion time, much shorter channels can be produced than are possible with mask control of channel length. These shorter channels allow much more current densities which again contribute to larger power dissipations. The shorter channel length also allows a larger transconductance gm to be attained in the V-FET and very considerably improves the frequency response and the device switching time.
Another very important factor in the geometry of the power MOSFET is the presence of the lightly doped N~ epitaxial layer close to the N+ substrate. When VGS is zero or negative and the drain is positive with respect to the source, the junction between the P-layer and the N~ layer is reverse-biased. The depletion region at the junction penetrates deep into the N~ layer and thus punch-through from drain to source are avoided. So relatively high VDS can be applied without any danger of device breakdown.
P-channel V-MOSFETs are also available. Their characteristics are similar to those of N-channel MOSFETs, except that the current directions and voltage polarities are reversed.