V-Groove MOS (VMOS)
This article explains in detail about the structure of VMOS with diagram, its characteristics, anisotropic etching and also the applications of VMOS.
To know the basics, click on the links given below.
TAKE A LOOK : SHORT CHANNEL MOS STRUCTURES
The structure of VMOS is similar to short-channel power FET that is constructed as a vertical structure. The operation is same as that of a Double-Diffused MOS (DMOS) device. Take a look at the figure below to know more about the VMOS structure. This device, like a DMOS device has a channel length which is set by the difference between the p-type and n+ diffusions.
In VMOS, the p-type epitaxial layer is lightly doped. Along with this, the space available for the expansion of the depletion region between the p+ diffused layer and the n+ substrate will cause a high breakdown voltage (BVDS) and a low drain capacitance. That is, the breakdown voltage will be almost greater than or equal to 50 Volts. Due to the heavily doped n+ substrate, the value of the drain series resistance is kept very small. The outer wall of the VMOS has an SiO2 insulation layer, which is covered by an aluminium layer. This aluminium layer acts as the gate for the device. In a VMOS device the thickness of the layer does not depend on the mask resolution. And due to the fact that a conventional mask lithographic process is used for its fabrication, the p-region is stretched as a channel above the substrate. Thus, it is easy to make a channel as short as 1micro meter, which is essential for high-speed MOSFETs.
Another unique feature of VMOS is the anisotropically-etched V-groove cut normally to the surface that extends through both the n+, p regions and penetrates slightly through the epitaxial region. Due to this, it is easier for the gate to overlay the p-diffusion which acts as the current conducting channel. The packing density of such devices on a chip is more as the MOSFET’s are formed on the slopes of the grooves.
The V-grooves are produced by an anisotropic or orientation – dependent etching (ODE) process. The etchant, which is usually KOH at (80 to 100)°C, attacks silicon very rapidly in the  crystallographic direction, but very slowly in the  direction. In the case of (100) oriented silicon substrates the result will be the production of V-shaped grooves that have (111) side walls as shown in the figure below. The angle of the (111) groove side walls with respect to the (100) silicon surface will be 54.74°. The width of the opening in the oxide layer controls the width of the grooves, W. The oxide layer width is used as an etching mask since SiO2 is attacked only very slowly by the etching solution.
The gate of the VMOS transistor is formed on the (111) faces of pyramidal-shaped crater, and extends around the perimeter of the pyramidal area. As a result, the width of the channel is very large compared with its length. The transconductance of the device will be high on a small area of the silicon chip due to the large width to length ratio. VMOS structures with large arrays of very many V-grooves gate structures are available with current ratings of up to several amperes.
- Hi-fi audio power amplifiers
- Broadband high-frequency amplifiers, and
- Switching power amplifiers which converts ac power sources into dc at arbitrary voltage.
Such power supplies made from VMOS will have lower cost, lighter weight, and smaller size than conventional power supplies.
There are Vertical DMOS structures with very large number of parallel connected cells in a rectangular or hexagonal pattern on a common n/n+ drain region. Such structures have continuous current ratings in excess of 25 A at voltages of up to 500 V. They also have a power handling capability of 12.5 kW. The drain-to-source on resistance values will be very less due to the very short channel length and very large total channel width. The large channel width is in the order of almost 1 million times greater than the channel length.