Once all components are fabricated on a single crystal wafer, they must be electrically isolated from each other. The problem is not encountered indiscrete circuits, because physically all components are isolated. There are two methods of isolation in Integrated circuits. They are

  • P-N  junction isolation and
  • Dielectric isolation

In this post we shall discuss p-n junction isolation.

The method of isolation is most compatible with the IC processing, that is, one extra processing step, other than required to fabricate IC, is required in isolation. Basically the method involves producing islands of n- type material surrounded by p-type material. Components are then fabricated in different n-type islands. The p-type material surrounding the islands is given the most negative p potential with respect to all parts of the wafer, thus each island and hence component is electrically isolated from the others by back-to-back diodes. The process step for p-n junction isolation are explained below:

1. One begins with the p-type substrate on which n-epitaxial layer is grown. If the component to be fabricated is transistor, then buried layer have to be formed before growing epi-layer. Figure [a] shows epi-layer growth over substrate without buried layer. The epi-layer is then covered with SiO2 layer.

2. A p-type diffusion is now performed from the surface of the wafer. Since this is to be performed in selected areas, an isolation mask is prepared prior to this diffusion. A long drive-in time is required for p-type diffusion so that the acceptor concentration is greater than the epi-layer donor concentration throughout the region of epi-layer. Thus the portion of wafer at the location of isolation diffusion is changed to p-type from the surface of wafer to the substrate. This is shown in the figure [b]. In other words, the substrate is extended toward the surface and acts as an isolation wall. This isolation wall causes the formation of p-n junction everywhere around the n-type islands except at the surface. If the substrate is connected to a voltage which is more negative than any of the n-region voltages, the diodes shown will be reversed biased and negligible current will flow. Thus isolation is achieved since any reverse biased p-n junction is associated with a depletion capacitance; this will have parasitic effect associated with junction, particularly, at high frequencies.

P-N Junction Isolation
P-N Junction Isolation

The main disadvantage of p-n junction isolations is as below:

  1. The time required for such isolation technique is considerably longer due to diffusion time taken, which is longer than any of other diffusions.
  2. Lateral diffusion is significant due to longer time taken by isolation diffusion, hence considerable clearance must be used for isolation regions.
  3. Isolation diffusion takes an area of the wafer surface which is significant portion of the chip area. From component density consideration, this area is wasted.
  4. P-N junction isolation method introduces significant parasitic capacitance which degrades circuit performance. The parasitic capacitance is introduced by isolation sidewall and bottom epitaxial substrate junction.

Several methods have been developed by manufacturers to avoid above problems. All of these methods circumvent the problems of large area and sidewall capacitance, but they suffer from the parasitic capacitance introduced by bottom epi-substrate junction. Dielectric isolation avoids this problem too.


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