TAKE A LOOK : INTRODUCTION TO PIC 167F877
TAKE A LOOK : PIC 16F877 – ARCHITECTURE AND MEMORY ORGANIZATION
TAKE A LOOK : REGISTER MEMORY ORGANIZATION IN PIC 16F877
TAKE A LOOK : EEPROM/FLASH MEMORY ORGANIZATION in PIC 16F877
Timer modules in PIC 16F877
The PIC 16F877 basically has three timer modules. These timer module terminals are also multiplexed with other functions for handling alternate functions. These timer modules are usually denoted by the symbols TIMER-0, TIMER-1, and TIMER-2.These modules help to perform various timing and counting functions inside the chip.
The main timing/counting features of Timer-0 module are given below.
- Timer-0 module has built in 8 bit timer/counter
- It can be easily readable/writable
- Built in 8 bit software programmable pre-scalar functions
- Easily select internal/external clock pulses
- Interrupt with overflow from the value FFh to 00h
- Edge selection for external clock pulse
The block diagram of timer-0 module is given in the figure below. The timer mode is normally selected by clearing the T0CS bit in the register. In Timer mode, when the Timer 0 Module increases with every instruction cycle, the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS in Counter mode. Timer 0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer 0 Source Edge Select bit, T0SE. Clearing bit T0SE selects the rising edge. The pre-scaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer.
TMR0 interrupt is activated only when the TMR0 register overflows from the value FFh to 00h. This overflow sets bit TMR0IF .The interrupt can be masked by clearing bit TMR0IE. Bit TMR0IF must be cleared in software by the Timer 0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the Processor from Sleep since the timer is shut-off during Sleep. The main registers associated with timer 0 module is shown in the below table.
TIMER 1 MODULE
Timer 1 module is a 16 bit timer/counter unit. That is, it consists of two 8 bit (8+8) registers (TMR1H, TMR1L) which read and write easily. TMR1 register is a pair of TMR1H and TMR1L and also its value increment its value from 0000h to FFFFh and rolls over to 0000h.
Timer 1 module basically operates in two different modes. They are
1) Timer mode
2) Counter mode
The operating mode of timer 1 module is selected by using the clock select bit (TMR1CS), in timer mode. The timer 1 increases on every instruction cycle. But in counter mode, it increases on every rising edge of the external clock input. Timer 1 pin can be enabled/disabled easily by setting/clearing the control bit (TMR1ON). This timer1 pin also has an internal reset input function. It can be generated by either of the two CCP modules.
The block diagram of timer1 module I given in the image below.
Timer 1 Operation in Timer Mode
The Timer mode can be easily selected by clearing the TMR1CS bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit, T1SYNC, has no effect since the internal clock is always in sync. Timer1 Operation in Synchronized
The synchronized Counter mode is selected by setting timer 1 synchronized counter select bit (TMR1CS). In this mode, the timer increments on every rising edge of clock input on pin RC1/T1OSI/CCP2 when bit T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared.
Timer1 Counter Operation
Timer 1 generally operates in two modes. Timer 1 may operate in either a Synchronous, or an Asynchronous mode, depending on the setting of the timer 1 synchronized counter select (TMR1CS) bit. When Timer1 is being incremented with an external source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment. Timer1 Operation in Synchronized
Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin RC1/T1OSI/CCP2 when bit T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared. If T1SYNC is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter.
In this configuration, during Sleep mode, Timer1 will not increment even if the external clock is present since the synchronization circuit is shut-off. The prescaler, however, will continue to increment.
Timer1 Operation in Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt-on-overflow which will wake-up the processor. However, special precautions in software are needed to read/write the timer. In Asynchronous Counter mode, Timer 1 cannot be used as a time base for capture or compare operations.
Timer 1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator, rated up to 200 kHz. It will continue to run during Sleep. It is primarily intended for use with a 32 kHz crystal. Below table shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure proper oscillator start-up. The capacitor selection for various frequencies is shown in the table below.
Register memory organization for timer 1 timer/counter module is given in the table below.
TIMER 2 Module
Timer 2 is an 8-bit timer with a prescaler and a postsaler. It can be used as the PWM (pulse width modulation) time base for the PWM mode of the CCP module(s). The block diagram of timer 2 module is given in the figure below.
The TMR2 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer 2 module has an 8-bit period register, PR2. The value of Timer 2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)). Timer 2 can be shut-off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption.
Register memory organization of timer 2 module is given in the table below.
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