Before knowing more about the master-slave flip flop you have to know more on the basics of a J-K flip flop and S-R flip flop. To know more about the flip flops, click on the link below. So in this article, we are learning in detail about Master Slave Flip Flops. We will see what are MS flip flops, how they operate, how to build a master slave flip flop circuit and many other things in detail.



Master-slave flip flop is designed using two separate flip flops. Out of these, one acts as the master and the other as a slave. The figure of a master-slave J-K flip flop is shown below.

Master Slave Flip Flop
Master Slave Flip Flop

From the above figure you can see that both the J-K flip flops are presented in a series connection. The output of the master J-K flip flop is fed to the input of the slave J-K flip flop. The output of the slave J-K flip flop is given as a feedback to the input of the master J-K flip flop. The clock pulse [Clk] is given to the master J-K flip flop and it is sent through a NOT Gate and thus inverted before passing it to the slave J-K flip flop.


When Clk=1, the master J-K flip flop gets disabled. The Clk input of the master input will be the opposite of the slave input. So the master flip flop output will be recognized by the slave flip flop only when the Clk value becomes 0. Thus, when the clock pulse males a transition from 1 to 0, the locked outputs of the master flip flop are fed through to the inputs of the slave flip-flop making this flip flop edge or pulse-triggered. To understand better take a look at the timing diagram illustrated below.

Master Slave J-K Flip Flop Timing Diagram
Master Slave J-K Flip Flop Timing Diagram

Thus, the circuit accepts the value in the input when the clock is HIGH, and passes the data to the output on the falling-edge of the clock signal. This makes the Master-Slave J-K flip flop a Synchronous device as it only passes data with the timing of the clock signal.

Wrap Up!

We’ve seen how a master slave flip flop operates, its representation and the wave diagrams.



  1. seetharaman

    Hi Sundar you may go through the article published earlier on this topic “FLIP FLOPS”. In a flip flop with the set pulse going high the output will go high. with reset pulse going high its out put will reset to low. A flip flop can be made to change only with one more additional information (positive or negative going pulse)that can be a continuous clock pulse. Please see “Triggering of Flip Flops” appeared earlier in this article. The preset, is the condition you want to set the flip flop during switch on of the system (prefered high or low out put status of flip flop)

  2. please explain in detail about basics of flip flop …,
    what is set, reset,preset,clock pulse.